In telecommunication systems, digital clock supplies are commonly used to generate local clock signals which are synchronized to incoming signals on transmission lines. A well-known technique employs a high-speed scaler driven by an internal free running local clock, whose modulus is varied in accordance with external control signals, to provide phase correction of the output clock signals of the scaler, thereby maintaining synchronization. The frequency of the internal free running clock pulses, is nominally a multiple of the clock pulses. Typically, when the scaler's division is changed, a phase correction of .+-.0.5 internal clock cycle occurs.
In a typical prior art system having flip-flops, the internal clock pulses are inverted under control of the external control signals, to provide this phase correction. This has the effect of momentarily interrupting the internal clock pulses applied to the flip-flops, by shifting their phase by 180.degree.. The result is that the scaler effectively responds to rising then falling edges of the internal clock pulses with each inversion, even though the output of the internal clock remains uninterrupted. In one such application, a divide-by-2 scaler, comprising a plurality of flip-flops, provides one output pulse for every two input clock pulses. As its modulus is changed from 2 to 1.5 or 2.5, it provides .+-.90 degree phase correction of the output clock signals. In high speed clock applications, where the internal clock runs at a frequency of typically 20 MHz or higher, interrupting the internal clock signal applied to the flip-flops tends to generate signal jitter on the output clock, due to settling times of the associated gates controlling the interruptions. Because of this jitter, the operation of the flip-flops can malfunction.